Fringe field switching mode LCD

ABSTRACT

Disclosed is a fringe field switching mode LCD. The disclosed comprises a first and a second transparent insulating substrates arranged opposite to each other with a predetermined distance, with a liquid crystal layer including a plurality of liquid crystal molecules interposed between them; a plurality of gate bus lines and data bus lines formed on the first transparent insulating substrate and arranged in a matrix form to define a unit pixel; a thin film transistor formed at the intersection of the gate bus line and the data bus line; a counter electrode disposed in each unit pixel, made of transparent conductor; and a pixel electrode arranged in each unit pixel to generate a fringe field with the counter electrode, being insulated with the counter electrode and made of transparent conductor and including a plurality of upper slits and lower slits symmetrical each other with respect to long side of the pixel with a predetermined tilted angle.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a fringe field switching modeliquid crystal display, and more particularly, to a fringe fieldswitching mode liquid crystal display capable of preventing degradationof screen quality due to color shift and disclination line.

[0003] 2. Description of the Related Art

[0004] It is well known that a Fringe Field Switching mode LiquidCrystal Display (hereinafter referred to as FFS mode LCD) has beenproposed in order to improve a low aperture ratio and transmittance ofIn Plane Switching mode LCD.

[0005]FIG. 1 is a plane view for showing a conventional FFS mode LCD. Asshown in FIG. 1, a plurality of gate bus lines 3 and data bus lines 7are arranged crossing with each other on a transparent insulatingsubstrate such as glass substrate (not shown). A counter electrode 2made of transparent conductor such as Indium Tin Oxide (ITO) is disposedin a pixel region defined by the lines 3, 7 crossing with each other.The counter electrode 2 generally has a plate shape and may have a combshape.

[0006] A common electrode line 10 is disposed in order to continuouslysupply common signals to the counter electrode 2. The common electrodeline 10 is parallel to the gate bus line 3, including a first part l0 abeing in contact with the upper part of the counter electrode 2 and apair of second parts l0 b extended from the first part l0 a to beparallel to the data bus line 7 and to be in contact with one side andthe other side of the counter electrode 2, respectively. The commonelectrode line 10 is generally formed at the same time when the gate busline 3 is formed.

[0007] A pixel electrode 9 made of transparent conductor such as ITO, isarranged in the pixel region, overlapping with the counter electrode 2.The pixel electrode 9 and the counter electrode 2 are electricallyinsulated by a gate insulating layer (not shown) . The pixel electrode 9has a comb shape including a plurality of branches 9 a arranged parallelto the data bus line 7 with the same distances and a bar 9 b connectingone ends of each branch 9 a.

[0008] A thin film transistor TFT is formed at the intersection of thegate bus line 3 and the data bus line 7. The thin film transistor TFTincludes a part of the gate bus line 3 i.e. a gate electrode, asemiconductor layer (not shown) formed on the gate electrode with a gateinsulating layer interposed, a source electrode 7 a disposed over oneside of the semiconductor layer and being in contact with the bar 9 b ofthe pixel electrode 9, and a drain electrode 7 b extended from the databus line 7 and disposed over the other side of the semiconductor layer.

[0009] Although it is not shown in the above, a color filter substrateis arranged opposite to the above array substrate with a distance longerthan that between the counter electrode 2 and the pixel electrode 9 andthen, a liquid crystal layer comprising a plurality of liquid crystalmolecules is interposed between the substrates.

[0010] According to the FFS mode LCD having the above structure, when apredetermined voltage is applied in the a counter electrode 2 and thepixel electrode 9, a fringe field is generated between the twoelectrodes and on the upper part thereof since the distance between thearray substrate and the color filter substrate is longer than thatbetween the electrodes 2,9. The fringe field has influence on all partsincluding the upper parts of the counter electrode 2 and of pixelelectrode 9, thereby driving all liquid crystal molecules on the upperparts of the electrodes 2,9 as well as those between the electrodes 2,9.

[0011] Therefore, the FFS mode LCD has a high aperture ratio since thecounter electrode and the pixel electrode are made of transparentconductor. Moreover, the FFS mode LCD has an improved transmittancesince liquid crystal molecules over the upper part of the electrodes aswell as those between the electrodes are driven.

[0012] However, in the FFS mode LCD, when a field is generated betweenthe counter electrode and the pixel electrode, liquid crystal moleculeshaving refractive anisotropy are arranged in one direction, therebygenerating color shift according to a viewing angle and degrading screenquality.

[0013] Therefore, it is essential to prevent the color shift in order toimprove screen quality of FFS mode LCD. As an effort to obtain improvedscreen quality, as shown in FIG. 2A, a pixel electrode 19 may havefracture slits S having a shape of “<” in a pixel. Alternatively, asshown in FIG. 2B, it has been proposed that the pixel electrode 19 has astructure that each pixel has a slit S in a slant direction symmetricalwith the adjacent pixel. In the above structures, an electric field isgenerated in one pixel or in two symmetrical directions between adjacentpixels, thereby compensating refractive anisotropy of liquid crystalmolecules and as a result, it is possible to prevent color shift.

[0014] However, according to the FFS mode LCD having compensatingelectrode structure to prevent color shift, when a positive liquidcrystal is applied, a disclination line is generated from the end ofpixel electrode. And, it is difficult to eliminate the disclinationline, thereby degrading screen quality. In particular, the disclinationline is generated more, when high voltage over driving voltage isapplied on panel and external pressure is applied on a voltage-appliedpanel.

SUMMARY OF THE INVENTION

[0015] Therefore, an object of the present invention is to provide a FFSmode LCD preventing generation of color shift and disclination line oreasily removing it when the disclination line is generated.

[0016] In order to accomplish the above object, FFS mode LCD of thepresent invention comprises: a first and a second transparent insulatingsubstrates arranged opposite to each other with a predetermineddistance, with a liquid crystal layer including a plurality of liquidcrystal molecules interposed between them; a plurality of gate bus linesand data bus lines formed on the first transparent insulating substrateand arranged in a matrix form to define a unit pixel; a thin filmtransistor formed at the intersection of the gate bus line and the databus line; a counter electrode disposed in each unit pixel, made oftransparent conductor; and a pixel electrode arranged in each unit pixelto generate a fringe field with the counter electrode, being insulatedwith the counter electrode and made of transparent conductor andincluding a plurality of upper slits and lower slits symmetrical eachother with respect to long side of the pixel with a predetermined tiltedangle.

[0017] The pixel electrode may further have a reference slit arrangedparallel to the gate bus line on the center of long side of pixel anddividing an upper slit and a lower silt. The upper slit and the lowerslit have a tilted angle below +45° and below −45° respectively, anddesirably, of ±2˜20° with respect to the axis dividing them. The slithas a structure that adjacent pixels in the same column have the sametilted angle and adjacent pixels in the same line have opposite tiltedangle.

[0018] And, the FFS mode LCD of the present invention include a firstand a second alignment layers respectively arranged on the top of innersides of the first and the second transparent insulating substrates anda first and a second polarizing plates respectively arranged on outersides of the first and the second transparent insulating substrates. Thefirst and the second alignment layers are rubbed parallel to the gatebus line when positive liquid crystals are applied, and rubbed parallelto the data bus line when negative liquid crystals are applied. Thefirst and the second polarizing plates have transmission axesperpendicular to each other and one of the axes has the same directionas rubbing direction of the alignment layer.

[0019] Also, the FFS mode LCD of the present invention further include acommon electrode line to apply common signals to the counter electrode.The common electrode line is arranged on the edge of pixel adjacent tothe gate bus line, being parallel to the gate bus line or arranged onthe center of each pixel, being parallel to the gate bus line.

[0020] The above objects, and other features and advantages of thepresent invention will become more apparent after reading the followingdetailed description when taken in conjunction with the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0021]FIG. 1 is a plane view for showing a conventional fringe fieldswitching mode LCD.

[0022]FIGS. 2A and 2B are plane views for showing a pixel electrode toeliminate color shift according to a conventional method.

[0023]FIGS. 3A and 3B are plane views for showing a fringe fieldswitching mode LCD according to an embodiment of the present invention.

[0024]FIGS. 4A and 4B are plane views for showing driving of fringefield switching mode LCD according to an embodiment of the presentinvention.

[0025]FIGS. 5 and 6 are plane views for showing a fringe field switchingmode LCD according to another embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0026] Referring to FIG. 3A, a plurality of gate bus lines 21 and databus lines 23 are cross arranged on a first transparent insulatingsubstrate (not shown) to define a unit pixel. A thin film transistor TFTis formed as a switching device at the intersection of the gate bus line21 and the data bus line 23. A counter electrode (not shown) is disposedin a plate form in the pixel. The counter electrode is made oftransparent conductor, desirably, ITO.

[0027] A pixel electrode 29, made of transparent conductor such as ITO,is disposed in the pixel to be insulated with the counter electrode andto be in contact with the thin film transistor TFT. The pixel electrode29 has a plurality of slits S1, S2 , S3 therein. A reference slit S1 isarranged parallel to the gate bus line 21 on the center of long side ofpixel and the upper slits S2 and the lower slits S3 are arranged with apredetermined tilted angle on the upper and the lower parts of thereference slit, respectively. The upper slit S2 and the lower slit S3have a tilted angle below ±45°, desirably, ±2˜20 °, with respect to thereference slit S1. The slits S1, S2, S3 have a width W of 1˜8 μm and thedistance L between slits is 1˜8 μm.

[0028] A common electrode line 30 is arranged parallel to the gate busline 21 on the edge of pixel adjacent to the gate bus line 21 in orderto apply common signals to the counter electrode. The common electrodelien 30 is in contact with a part of the counter electrode, overlappedwith a part of the pixel electrode 29.

[0029] Although it is not shown in the drawings, a color filtersubstrate having a structure that elements such as black matrix andcolor filter are formed on a second transparent insulating substrate, isarranged with a predetermined distance from the above array substrate.And a liquid crystal layer (not shown) including a plurality of positiveor negative liquid crystal molecules is interposed between thesubstrates. Also, a first and a second alignment layers are formed onthe inner sides of the array substrate and the color filter substrateand a first and a second polarizing plates are formed on the outer sidesof the array substrate and the color filter substrate.

[0030] Herein, The first and the second alignment layers are rubbedparallel to the gate bus line 21 when positive liquid crystals areapplied, and rubbed parallel to the data bus line 23 when negativeliquid crystals are applied. The transmittance axes of the first and thesecond polarizing plates are formed perpendicular to each other to beoperated in normally black mode, and one of the axes is parallel torubbing direction of the alignment layer.

[0031] Referring to FIG. 3B, the pixel electrode 29 may have only upperslits S2 and lower slits S3, without a reference slit. In this case, apair of dummy slits S4 having a triangular shape are additionally formedon adjacent regions of the upper slit S2 and the lower slit S4.

[0032] The operation of the above FFS mode LCD will be described in thefollowing.

[0033] Referring to FIG. 4A, when voltage is not applied, liquid crystalmolecules 100 a, 100 b, 100 c are arranged, the long side thereof beingparallel to rubbing axis R.

[0034] When voltage is applied, a fringe field is generated due tovoltage difference between counter electrode and pixel electrode,thereby rotating clockwise liquid crystal molecules 100 b disposed onthe upper part of the reference slit S1 and counterclockwise liquidcrystal molecules 100 c disposed on the lower part thereof. However, thereference slit S1 of pixel electrode has no change in the position. Inthe drawings, code 100 b′ indicates liquid crystal molecules rotatedclockwise and 100 c′ liquid crystal molecules rotated counterclockwise.

[0035] When there is no reference slit, liquid crystal molecules are notrotated on the axis of symmetry of upper slits and lower slits, however,liquid crystal molecules 100 b on the upper part thereof are rotatedclockwise and liquid crystal molecules on the lower part thereof arerotated counterclockwise.

[0036] Therefore, as shown in FIG. 4B, liquid crystal molecules arearranged in two directions in one pixel, thereby compensating refractiveanisotropy of liquid crystal molecules and preventing color shift. And,the pixel electrode has no fracture therein, thereby preventinggeneration of disclination line and if they are generated, it is easy toeliminate them.

[0037] As a result, FFS mode LCD of the present invention has improvedscreen quality by preventing color shift and by preventing or easilyeliminating disclination lines.

[0038] While, various modifications of the embodiment are described inthe following.

[0039] In the above embodiment, upper slits have a tilted angle of +θand lower slits have a tilted angle of −θ. However, the same effect isobtained in the contrary i.e. upper slits have a tilted angle of −θ andlower slits have a tilted angle of +θ.

[0040] And, referring to FIG. 5, in the pixel electrode 29, upper slitsS2 and lower slits S3 have the structure that adjacent pixels have thesame tilted angle in the same column and opposite tilted angle in thesame line.

[0041] Further, referring to FIG. 6, the common electrode line 30 isarranged parallel to the gate bus line under the axis dividing the pixelinto upper and lower parts by the direction of electric field, that is,a reference slit S1 of pixel electrode 29.

[0042] As described above, according to the present invention, a pixelelectrode comprises a plurality of slits, wherein the silts have nofracture and the tilted angle thereof is symmetrical each other withrespect to a reference slit, thereby preventing color shift andpreventing or easily eliminating disclination line. As a result, the FFSmode LCD has improved screen quality.

[0043] Although the preferred embodiment of this invention has beendisclosed for illustrative purpose, those skilled in the art willappreciate that various modifications, additions and substitutions arepossible, without departing from the scope and spirit of the invention.

What is claimed is
 1. A fringe field switching mode LCD comprising: afirst and a second transparent insulating substrates arranged oppositeto each other with a predetermined distance, with a liquid crystal layerincluding a plurality of liquid crystal molecules interposed betweenthem; a plurality of gate bus lines and data bus lines formed on thefirst transparent insulating substrate and arranged in a matrix form todefine a unit pixel; a thin film transistor formed at the intersectionof the gate bus line and the data bus line; a counter electrode disposedin each unit pixel, made of transparent conductor; and a pixel electrodearranged in each unit pixel to generate a fringe field with the counterelectrode, being insulated with the counter electrode and made oftransparent conductor and including a plurality of upper slits and lowerslits symmetrical each other with respect to long side of the pixel witha predetermined tilted angle.
 2. The fringe field switching mode LCDaccording to claim 1, wherein the pixel electrode further comprising areference slit dividing the upper slit and the lower slit and arrangedparallel to the gate bus line on the center of long side of pixel. 3.The fringe field switching mode LCD according to claim 1, wherein thetilted angle of upper slit and lower slit is below +45° and below −45°with respect to the axis dividing upper and lower slits.
 4. The fringefield switching mode LCD according to claim 3, wherein the tilted angleof upper slit and lower slit is ±2˜20° with respect to the axis dividingupper and lower silts.
 5. The fringe field switching mode LCD accordingto claim 1, wherein a width of the slit is 1˜8μm and the distancebetween slits is 1˜8μm.
 6. The fringe field switching mode LCD accordingto claim 1, wherein slits of pixel electrode have the structure thatadjacent pixels in the same column have the same tilted angle andadjacent pixels in the same line opposite tilted
 7. The fringe fieldswitching mode LCD according to claim 1, wherein further comprising afirst and a second alignment layers respectively arranged on the top ofinner sides of the first and the second transparent insulatingsubstrates, and a first and a second polarizing plates respectivelyarranged on outer sides of the first and the second transparentinsulating substrates.
 8. The fringe field switching mode LCD accordingto claim 7, wherein the first and the second alignment layers are rubbedparallel to a gate bus line when positive liquid crystals are appliedand parallel to a data bus line when negative liquid crystals areapplied.
 9. The fringe field switching mode LCD according to claim 7,wherein the first and the second polarizing plates have transmissionaxes perpendicular to each other and one of the axes has the samedirection as rubbing direction of the alignment layer.
 10. The fringefield switching mode LCD according to claim 1, wherein furthercomprising a common electrode line in order to apply common signals tothe counter electrode.
 11. The fringe field switching mode LCD accordingto claim 10, wherein the common electrode line is arranged on the edgeof pixel adjacent to gate bus line, parallel to the gate bus line. 12.The fringe field switching mode LCD according to claim 10, wherein thecommon electrode line is arranged on the center of each pixel, parallelto the gate bus line.
 13. The fringe filed switching mode LCDcomprising: a first and a second transparent insulating substratesarranged opposite to each other with a predetermined distance, with aliquid crystal layer including a plurality of liquid crystal moleculesinterposed; a plurality of gate bus lines and data bus lines formed onthe first transparent insulating substrate and arranged in a matrix formto define a unit pixel; a thin film transistor formed at theintersection of the gate bus line and the data bus line; a counterelectrode disposed in each unit pixel, made of transparent conductor; apixel electrode arranged in each unit pixel to generate a fringe fieldwith the counter electrode, being insulated with the counter electrodeand made of transparent conductor and including a plurality of upperslits and lower slits symmetrical each other with respect to long sideof the pixel with a predetermined tilted angle; a first and a secondalignment layers respectively arranged on the top of inner sides of thefirst and the second transparent insulating substrates; and a first anda second polarizing plates respectively arranged on the outer sides ofthe first and the second transparent insulating substrates.